ICSES Transactions on Computer Hardware and Electrical Engineering

Manuscript In Press (Unedited Version)


Latest trends in Hardware Verification | Accepted Manuscript

a Intel Corporation, San Jose, USA.

Highlights and Novelties


1. Prioritization strategies on chip verification

2. How coverage driven random stimuli creates hard to reach corner-cases

3. Simulation based vs property based (assertion/formal) techniques


Manuscript Abstract
Chip design complexity has grown in the past two decades at an exponential rate. In this era of multi-million gate System on Chip (SOC) designs, the verification activity consumes more than 70% of the total project effort. The cost of a design bug and subsequent re-spin of the chip is in the order of tens of millions of dollars. However, exhaustively verifying the design for all possible input and state-space conditions is a seemingly impossible task. This paper has tried to capture the state of the art verification methodologies used for present day ASIC and FPGA design. It explains the philosophy behind coverage driven constraint random verification, something that has revolutionized the chip verification industry. The paper also talks about two recently introduced techniques, namely assertion and formal verification. Compared to the traditional simulation based verification methodologies, formal and assertion methods provide a more complete coverage, but at the expense of more compute resource and time.

Keywords
 Chip Design   Constraint Random Verification   Assertion   Formal Verification 

Copyright
© Copyright was transferred to International Computer Science and Engineering Society (ICSES) by all the Authors.

Cite this manuscript as
Joydeep Bhattacharyya, "Latest trends in Hardware Verification," ICSES Transactions on Computer Hardware and Electrical Engineering (ITCHEE), In Press, pp. 1-2, Mar. 2018.

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